Modern data communication and networking systems make extensive use of synchronous RAM for data processing. FIG. 1 shows a memory architecture of a conventional networking application (e.g., a line card) using synchronous RAM to perform a variety of functions under the control of a processor. In the line card of FIG. 1, data packets from a network are received by the processor and stored in a high-speed memory called a packet buffer. Subsequent processing of the data packets relies on data and instructions that are stored in the other memory structures shown in FIG. 1, such as a lookup table, a queue management memory, a statistics buffer and a policy buffer.
Each of these memories may use synchronous RAM of one type or another. Synchronous RAM is random access memory in which read and write operations are synchronized by the transitions of periodic signals called clock signals. In single data rate (SDR) synchronous RAM, data is transferred on each rising (or falling) edge of a clock signal. In order to achieve higher data transfer rates and maximize data throughput, double data rate (DDR) devices transfer data on both the rising and falling edges of the clock signal (or on the rising or falling edges of two separate clock signals). In order to avoid read/write data collisions on the data bus, separate buses can be provided for reading and writing data, and each bus can operate at double data rates to yield a quad data rate (QDR™) device. A further speed enhancement is achieved with burst-mode read and write operations. In burst-mode, the address provided to the memory specifies the starting point for a burst of data words, to or from the memory, which includes the addressed location and some number of contiguous locations.
The packet buffer is the most demanding memory requirement in the line card of FIG. 1 because data packets can be quite long and the buffer must be very deep to accommodate the network data rate. Packet buffers may use DDR, QDR™ or burst-mode QDR™ RAM. Depending on the specific application, the lookup table, the queue management memory, the statistics buffer and the policy buffer may use DDR, QDR™ or burst-mode QDR™ RAM to keep pace with the packet buffer.
Read and write operations in such memories may be characterized by a latency period. Read latency is the time period between the time that an address of a memory location is specified and the time that data is read from the memory location specified by the address. Write latency is the time period between the time that an address of a memory location is specified and the time that data is actually written to the memory location specified by the address. The latency period, measured in clock cycles, arises from the need to perform one or more intermediate operations before the data can be accessed. For example, before data can be written to a memory address, the address must be decoded and the data must be transferred from an external input port to an internal data register.
FIG. 2 illustrates an interface of a conventional synchronous RAM device. The address input (ADD) is an n-bit wide bus. The data input (D) is an m-bit wide bus, as is the data output (Q). A read enable (RE) signal enables a data read operation. A write enable (WE) signal enables a data write operation. Clock signals k and k# synchronize the READ/WRITE operations.
FIG. 3 illustrates a READ/WRITE timing diagram of a conventional synchronous RAM device, shown with a read latency of 1½ clock cycles and a write latency of 1 clock cycle. Read address A at address input ADD is latched into an address register at time to. Address input ADD is idle at time t1 while address A is processed. Similarly, write address B at address input ADD is latched into the address register at time t2 and address input ADD is idle at time t3 while address B is processed. The sequence is repeated from time t4 to time t7 for addresses C and D.
Because the data rates are high and the processing is complex, multiple banks of synchronous RAM may be required to manage the data traffic. As a result, many address lines are needed to manage the memory and a correspondingly large number of connection points must be provided on the system processor. This creates several problems. First, the internal design of the processor becomes very difficult, costly and time consuming. Second, the layout of the line-card becomes very difficult, costly and time-consuming. Extra circuit layers may be required to accommodate the required line routing. Each additional layer adds to the manufacturing cost of the board and decreases its reliability.